Digital processors are used in modern communication devices to perform complex signal processing while adhering to reasonable power and size constraints. In order to communicate information to another radio, digital signals are converted to analog signals. This conversion process is performed by a digital-to-analog converter (DAC).
The frequency representation of a digital signal consists of an infinite number of replicas of the desired analog signal, as shown in FIG. 1. The replicas are separated in the frequency domain by fs′ where fs′ is the frequency of the digital clock that times the digital signal. These replicas are undesirable after conversion to the analog domain. Several approaches are used to remove these replicas in the analog domain, including analog low pass filtering, interpolation, high order sample-and-hold circuits, and combining the output of multiple DACs that have offset clocks.
An analog low pass filter with a stop band that starts at fs′/2 removes all replicas except the one centered at zero frequency (DC). The pass band of the analog low pass filter must be as large as the desired signal bandwidth. If the desired signal bandwidth is close to fs′/2, as in FIG. 1, then there is only a small region for the filter to transition from pass band to stop band. A short transition region requires a highly selective filter, which means that the filter must be physically large and complex to design.
Interpolation in the digital domain consists of up-sampling the signal, then digitally filtering the additional images generated by the up-sampling process. As shown in FIG. 2 for an up-sampling ratio of four, the up-sampling clock operates at a faster rate than the digital clock that clocks the digital data input to the interpolator. Thus, the sampling at the output of the interpolator is higher, so that the replicas of the signal are spaced further apart in the frequency domain. This is so, because the spacing between the replicas is fs′. Since the replicas are spaced further apart, the selectivity of the low pass filter at the DAC output can be relaxed. This is shown in FIG. 3. Thus, interpolation is equivalent to sampling a signal faster than the Nyquist rate, where the Nyquist rate is twice a signal's baseband bandwidth.
The manner in which the DAC generates the analog signal shapes the effective frequency response of the DAC. A DAC may apply a zero-order hold, a first-order hold, a second-order hold, etc. With zero-order hold, the signal is held constant for one clock period (curve a of FIG. 4). With a first-order hold a straight line is generated between two consecutive samples (curve b of FIG. 4). With a second-order hold, a quadratic curve connects three consecutive samples (curve c of FIG. 4). The frequency responses of the zero-order hold, the first-order hold, and the second-order hold are
      sinc    ⁡          (                        π          ⁢                                          ⁢          f                          f          s                    )        ,            sinc      2        ⁡          (                        π          ⁢                                          ⁢          f                          f          s                    )        ,      and    ⁢                  ⁢                  sinc        3            ⁡              (                              π            ⁢                                                  ⁢            f                                f            s                          )              ,respectively. These functions are graphed in FIG. 5, which shows that the functions have nulls at the center of all undesired replicas.
Each hold order requires a differentiator in the digital domain and an integrator in the analog domain. For example, a single-order hold requires two digital differentiators and two analog integrators. The frequency response of the high order holds is not flat over the desired signal's pass band, so some form of compensation is required. Further, high order holds, of themselves, do not significantly relax the low pass filter requirements since their frequency responses do not provide sufficient stop band attenuation near fs′/2. However, high order holds can be used with interpolation to relax low pass filter requirements. This is so because interpolation confines more of the replicas' signal energy to the vicinity of the nulls of the high order hold frequency responses.
Multiphase clocking involves summing the output of parallel DACs, with each DAC clock offset from the others. Multiple DACs with different clock phases can be used to provide additional nulls in the frequency response. The same input signal is fed to each of the DACs. The additional nulls can be used to attenuate images beyond that achievable by a zero-order hold frequency response.
Ideally, transmitters should integrate the DAC and frequency up-conversion functions into a single integrated chip. The low pass filters required in all of the above-described approaches do not integrate well onto chips due to their large area and a lack of precise passive devices. In order to integrate the DAC and frequency up-conversion functions, all undesired replicas at the DAC output need to be significantly attenuated with a small integrated low pass filter—which implies low selectivity—or no filter at all.
If the undesired replicas are not significantly attenuated, non-linear action in the up-conversion process will result in inter-modulation distortion (IMD) falling within the pass band. The replicas and their IMD components outside the pass band must be filtered after up-conversion by a highly selective RF band pass filter, which is typically larger and more complex than the low pass filter it replaces.
In summary, high order sample-and-hold using analog integrators requires passive and possibly active components between the DAC and up-conversion mixer. As with a highly selective low pass filter, additional passive components do not integrate well into a single chip solution. Interpolation requires the clock rate to be increased by the up-sampling ratio. A large up-sampling ratio is required to increase the attenuation bandwidth of the images. However, a very fast clock is unrealistic, especially with the large signal bandwidths typical of base station transmitters in a wireless communication system. Parallel DACs fed with the same digital signal have been used to attenuate certain images. This approach may provide notches in the frequency response which can be collocated with replicas. However, these notches have a fixed attenuation bandwidth which may not be sufficiently wide for the large signal bandwidths that are typical of signals at a base station.
Therefore, what is needed is a combination of digital-to-analog conversion and frequency up-conversion that suppresses undesired replicas in the spectra of a signal, that does not require a higher speed clock, that does not require high order filtering, and that can be integrated onto a single integrated circuit chip.